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RCA란 Ripple Carry Adder의 약자로 1비트 가산기에서 생성된 carry(자리 올림수)를 ripple(물결)처럼 계속 넘기는 것을 반복한다고 해서 Ripple Carry Adder라는 이름이 붙여졌다. 

4bit RCA의 구성

각 비트의 합은 1-bit Full Adder로 연산이 된다 LSB(Least Significant Bit)의 연산에서 Carry in을 받고 다음 Full Adder에게 Carry out을 넘겨준다. 

다음 비트는 LSB의 연산에서 나온 Carry out을 Carry in을 입력으로 받고 다음 해당 비트의 Carry out을 다음 비트에 넘겨준다. 이 과정은 MSB(Most Significant Bit)까지 반복을 하고 MSB의 Carry out은 해당 RCA 4비트의 최종적 Carry out이 된다. 

32bit RCA의 경우는 위 과정을 32번 반복한다고 생각하면 된다. 

32bit RCA RTL view

32bit RCA Verilog HDL code

module rca_32bit(a, b, Cin, Sum, Cout);
	input [31:0] a, b;
	input Cin;
	output [31:0] Sum;
	output Cout;
	wire [2:0] Carry;
	
	rca_8bit rca_8bit01(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .Sum(Sum[7:0]), .Cout(Carry[0]));
	rca_8bit rca_8bit02(.a(a[15:8]), .b(b[15:8]), .Cin(Carry[0]), .Sum(Sum[15:8]), .Cout(Carry[1]));
	rca_8bit rca_8bit03(.a(a[23:16]), .b(b[23:16]), .Cin(Carry[1]), .Sum(Sum[23:16]), .Cout(Carry[2]));
	rca_8bit rca_8bit04(.a(a[31:24]), .b(b[31:24]), .Cin(Carry[2]), .Sum(Sum[31:24]), .Cout(Cout));
endmodule

module HalfAdder(a, b, Sum, Cout);
   input a, b;
   output Sum, Cout;
   
   assign Sum = a ^ b;
   assign Cout = a & b;
endmodule

module FullAdder(a, b, Cin, Sum, Cout);
	input a, b, Cin;
	output Sum, Cout;
	wire Sum01, Carry01, Carry02;
	
	HalfAdder HA01(.a(a), .b(b), .Sum(Sum01), .Cout(Carry01));
	HalfAdder HA02(.a(Sum01), .b(Cin), .Sum(Sum), .Cout(Carry02));
	
	assign Cout = Carry01 | Carry02;
endmodule

module rca_4bit(a, b, Cin, Sum, Cout);
	input [3:0] a, b;
	input Cin;
	output [3:0] Sum;
	output Cout;
	wire [2:0] Carry;
	
	FullAdder FA01(.a(a[0]), .b(b[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(Carry[0]));
	FullAdder FA02(.a(a[1]), .b(b[1]), .Cin(Carry[0]), .Sum(Sum[1]), .Cout(Carry[1]));
	FullAdder FA03(.a(a[2]), .b(b[2]), .Cin(Carry[1]), .Sum(Sum[2]), .Cout(Carry[2]));
	FullAdder FA04(.a(a[3]), .b(b[3]), .Cin(Carry[2]), .Sum(Sum[3]), .Cout(Cout));
endmodule

module rca_8bit(a, b, Cin, Sum, Cout);
	input [7:0] a, b;
	input Cin;
	output [7:0] Sum;
	output Cout;
	wire Carry;
	
	rca_4bit rca_4bit01(.a(a[3:0]), .b(b[3:0]), .Cin(Cin), .Sum(Sum[3:0]), .Cout(Carry));
	rca_4bit rca_4bit02(.a(a[7:4]), .b(b[7:4]), .Cin(Carry), .Sum(Sum[7:4]), .Cout(Cout));
endmodule

필자는 Half Adder로 Full Adder 모듈을 만들었다 (뇌피셜 - 대체적으로 이렇게 만들더라). 그다음 Full Adder 4개를 이용하여 4비트 RCA 모듈을 만들었다. 그다음 4비트 RCA 2개를 이용해 8비트 RCA를 만들었다. 

32비트 RCA를 Full Adder로 만드는 법은 Full Adder 32개를 이어주는 방법이 가장 쉽고 직관적인 방법이다. 

32bit RCA Verilog HDL code (with 32 Full Adders)

module rca_32bit(a, b, Cin, Sum, Cout);
	input [31:0] a, b;
	input Cin;
	output [31:0] Sum;
	output Cout;
	wire [2:0] Carry;
	
	
	fulladder fulladder_0(.a(a[0]), .b(b[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(Carry[0]));			//connect input and output, it generateSum Carry 
	fulladder fulladder_1(.a(a[1]), .b(b[1]), .Cin(Carry[0]), .Sum(Sum[1]), .Cout(Carry[1]));		//connect input Cin with Carry that generated Carry in 0-bit poSumition
	fulladder fulladder_2(.a(a[2]), .b(b[2]), .Cin(Carry[1]), .Sum(Sum[2]), .Cout(Carry[2]));		
	fulladder fulladder_3(.a(a[3]), .b(b[3]), .Cin(Carry[2]), .Sum(Sum[3]), .Cout(Carry[3]));
																															//4bit adder
	fulladder fulladder_4(.a(a[4]), .b(b[4]), .Cin(Carry[3]), .Sum(Sum[4]), .Cout(Carry[4]));
	fulladder fulladder_5(.a(a[5]), .b(b[5]), .Cin(Carry[4]), .Sum(Sum[5]), .Cout(Carry[5]));
	fulladder fulladder_6(.a(a[6]), .b(b[6]), .Cin(Carry[5]), .Sum(Sum[6]), .Cout(Carry[6]));
	fulladder fulladder_7(.a(a[7]), .b(b[7]), .Cin(Carry[6]), .Sum(Sum[7]), .Cout(Carry[7]));
																															//4bit adder
	fulladder fulladder_8(.a(a[8]), .b(b[8]), .Cin(Carry[7]), .Sum(Sum[8]), .Cout(Carry[8]));
	fulladder fulladder_9(.a(a[9]), .b(b[9]), .Cin(Carry[8]), .Sum(Sum[9]), .Cout(Carry[9]));
	fulladder fulladder_10(.a(a[10]), .b(b[10]), .Cin(Carry[9]), .Sum(Sum[10]), .Cout(Carry[10]));
	fulladder fulladder_11(.a(a[11]), .b(b[11]), .Cin(Carry[10]), .Sum(Sum[11]), .Cout(Carry[11]));
																															//4bit adder
	fulladder fulladder_12(.a(a[12]), .b(b[12]), .Cin(Carry[11]), .Sum(Sum[12]), .Cout(Carry[12]));
	fulladder fulladder_13(.a(a[13]), .b(b[13]), .Cin(Carry[12]), .Sum(Sum[13]), .Cout(Carry[13]));
	fulladder fulladder_14(.a(a[14]), .b(b[14]), .Cin(Carry[13]), .Sum(Sum[14]), .Cout(Carry[14]));
	fulladder fulladder_15(.a(a[15]), .b(b[15]), .Cin(Carry[14]), .Sum(Sum[15]), .Cout(Carry[15]));
																															//4bit adder
	fulladder fulladder_16(.a(a[16]), .b(b[16]), .Cin(Carry[15]), .Sum(Sum[16]), .Cout(Carry[16]));
	fulladder fulladder_17(.a(a[17]), .b(b[17]), .Cin(Carry[16]), .Sum(Sum[17]), .Cout(Carry[17]));
	fulladder fulladder_18(.a(a[18]), .b(b[18]), .Cin(Carry[17]), .Sum(Sum[18]), .Cout(Carry[18]));
	fulladder fulladder_19(.a(a[19]), .b(b[19]), .Cin(Carry[18]), .Sum(Sum[19]), .Cout(Carry[19]));
																															//4bit adder
	fulladder fulladder_20(.a(a[20]), .b(b[20]), .Cin(Carry[19]), .Sum(Sum[20]), .Cout(Carry[20]));
	fulladder fulladder_21(.a(a[21]), .b(b[21]), .Cin(Carry[20]), .Sum(Sum[21]), .Cout(Carry[21]));
	fulladder fulladder_22(.a(a[22]), .b(b[22]), .Cin(Carry[21]), .Sum(Sum[22]), .Cout(Carry[22]));
	fulladder fulladder_23(.a(a[23]), .b(b[23]), .Cin(Carry[22]), .Sum(Sum[23]), .Cout(Carry[23]));
																															//4bit adder
	fulladder fulladder_24(.a(a[24]), .b(b[24]), .Cin(Carry[23]), .Sum(Sum[24]), .Cout(Carry[24]));
	fulladder fulladder_25(.a(a[25]), .b(b[25]), .Cin(Carry[24]), .Sum(Sum[25]), .Cout(Carry[25]));
	fulladder fulladder_26(.a(a[26]), .b(b[26]), .Cin(Carry[25]), .Sum(Sum[26]), .Cout(Carry[26]));
	fulladder fulladder_27(.a(a[27]), .b(b[27]), .Cin(Carry[26]), .Sum(Sum[27]), .Cout(Carry[27]));
																															//4bit adder
	fulladder fulladder_28(.a(a[28]), .b(b[28]), .Cin(Carry[27]), .Sum(Sum[28]), .Cout(Carry[28]));
	fulladder fulladder_29(.a(a[29]), .b(b[29]), .Cin(Carry[28]), .Sum(Sum[29]), .Cout(Carry[29]));
	fulladder fulladder_30(.a(a[30]), .b(b[30]), .Cin(Carry[29]), .Sum(Sum[30]), .Cout(Carry[30]));
	fulladder fulladder_31(.a(a[31]), .b(b[31]), .Cin(Carry[30]), .Sum(Sum[31]), .Cout(Cout));
	
endmodule